The present invention relates generally to methods for displaying logic signals, and more specifically to a method of displaying a logic signal on a raster scan type display device.
In various kinds of electronic apparatus, logic signal processing techniques are performed by microprocessors and computers. Oscilloscopes, logic probes and logic analyzers are utilized for developing, calibrating and trouble-shooting an electronic apparatus using these logic techniques. A logic analyzer, in particular, is an ideal measurement instrument for such electronic apparatus because it can store multi-channel input logic signals (data) in a random access acquisition memory and display representations of the stored signals on a display means, such as a cathode ray tube (CRT), so that the signals can be measured. The logic analyzer is a convenient measurement instrument to use when a multi-channel measurement is required. There are two display modes typically utilized by logic analyzers. In a timing display mode the logic signal is displayed as a signal waveform, while in a state display mode the stored data is displayed as alphanumeric words, in binary, octal or hexadecimal form.
A raster scan type display device is suitable as a display means for logic analyzers since the raster scan type display device can display the data in both the timing and state display modes, in a flicker free fashion, even if a large amount of information is displayed.
Many conventional techniques have been proposed for displaying longer waveforms on a limited display area of a CRT. One such technique is the compression of the time (horizontal) axis of the display screen by changing the slope of an X-axis sweep signal to decrease the horizontal sweep rate. However, this technique is possible only in an X-Y type display CRT wherein the logic signal and a ramp or stair-case signal are supplied to the Y and X-axes of the display device, respectively. In a raster scanned CRT the number of FONTs (display segments) in a display area is predetermined and the number of bits in each FONT is also predetermined, and a raster scan type display cannot utilize the above-mentioned time-axis compression technique. Even if the number of FONTs in the display area is increased, the displayed waveforms are small as a result of the time-axis compression technique and it is difficult to observe the displayed waveforms in detail.
Another conventional technique involves display of a single channel logic signal with a plurality of separated traces (multi-trace method). However, the display area available for other channels is limited, making it difficult to display many channel signals at the same time.
Japanese Published Examined patent application No. 55-46579 discloses a logic analyzer which measures the time between transitions of an input logic signal in order to acquire the signal. This method may save memory capacity associated with an acquisition memory circuit since the acquired logic signal is compressed in time, but this method requires the use of an additional circuit in order to measure the elapsed time (period) between transitions. As a result, the construction of such a logic analyzer becomes significantly more complex.
Another conventional technique for displaying more waveform information on a CRT comprises reducing the amplitude of each logic waveform. However, it is then difficult to measure the logic waveforms as a result of the reduction in the amplitude. In addition, a scroll mode has been utilized for displaying long logic waveforms on a screen by gradually scrolling the waveforms across the screen, but this mode does not permit viewing the entire waveform at one time.